Technical Field
Embodiments of the present disclosure relate to techniques for driving a Field-Effect Transistor (FET).
Description of the Related Art
FIG. 1 shows a typical half-bridge arrangement 20 comprising two electronic switches SW1 and SW2, such as n-channel power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor), connected in series between a supply voltage Vdd and a ground GND.
Usually, the switches SW1 and SW2 are closed alternatively in order to connect the output OUT of the half-bridge arrangement 20, i.e., the intermediate point between the switches SW1 and SW2, either to the voltage Vdd or to ground GND.
For this purpose, the half-bridge is driven as a function of two drive signals DRV1 and DRV2, which are connected (e.g., directly) to the control gates of the switches SW1 and SW2, respectively.
Specifically, in order to correctly drive the control gates, usually a high-side driver 2001 is used to generate the drive signal DRV1 for the high-side switch SW1 as a function of a first control signal IN1, and a low-side driver 2002 is used to generate the drive signal DRV2 for the low-side switch SW2 as a function of a control signal IN2.
The control signal IN2 corresponds often to an inverted version of the signal IN1 (or vice versa), i.e., the signal IN2 is low when the signal IN1 is high and vice versa. For example, in FIG. 1 is used an inverter 202 which receives at input the signal IN1 and provides at output the signal IN2.
The output OUT of the half-bridge arrangement 20 may be used to drive a load. For example, in FIG. 1, the half-bridge arrangement 20 drives a motor M1 connected between the output OUT of the half-bridge arrangement 20 and ground GND.
Conversely, FIG. 2 shows an example in which two half-bridge arrangements 20a and 20b are used to drive a linear motor M2, such as a voice coil motor, connected between the output OUTa of the first bridge arrangement 20a and the output OUTb of the second bridge arrangement 20b. As well known to those of skill in the art, in this case, also the rotation direction of the motor M2 may be controlled by applying appropriate control signals INa and INb to the half-bridge arrangements 20a and 20b.
Finally, FIG. 3 shows an example in which three half-bridge arrangements 20a, 20b and 20c are used to drive a three phase motor M3, such as a spindle motor, connected between the outputs OUTa, OUTb and OUTc of the half-bridge arrangements 20a, 20b and 20c.
For example, typically the control signals IN1 and IN2 correspond to pulse width modulated (PWM) signals, i.e., signals with a fixed frequency and a variably duty cycle.
Accordingly, in the examples considered, the actuation of a load, in particular inductive loads (such as motors), requires at least one half-bridge arrangement 20 able to reproduce the profile of at least one input signal IN at the terminals of the load.
However, there are limitations for the implementation of the half-bridge arrangement 20 and in particular the drivers 2001 and 2002 that should be taken into account.
A first problem may arise in case both switches SW1 and SW2 are switched on (i.e., conductive) at the same time. This condition is known as cross conduction and should be avoided, because it may be destructive for the switches SW1 and SW2. In order to avoid this problem, dead times may be introduced, in which both power MOSFETs SW1 and SW2 are switched off. However, such dead times may result in a degradation of the voltage profile both in terms of distortions and efficiency.
A second problem may relate to EMI (Electromagnetic interference) emissions during the commutation edges. The EMI emission can be reduced by controlling the slope of the edges. Both the controlled slope and dead times contribute to define a minimum width of the PWM input signal that can be actuated without distortions.
Accordingly, the optimization of power MOSFET driving requires performing a specific control of the gates during the switch-on and switch-off process.
FIG. 4 shows a qualitative representation of the gate-source charge curve VGS in relation to charge applied to the gate of a power MOSFET.
When the power MOSFET has to be turned on, the respective driver 200 should quickly charge the gate to pass a first region R1, usually called sub threshold region.
In a second region R2, usually called saturation region or Miller plateau, the current/charge injected into the gate does not increase significantly the gate voltage and the quantity of current/charge injected may be used to define the slope of the switching node edge. Accordingly, during this phase, the current may be controlled in order to reduce the generation of EMI interferences.
The following third region R3, usually called linear region, represents a transition region until the minimum switch-on resistance Ron condition is reached.
In the case of power MOSFETs, it is preferably to have a sequential control to correctly manage the different regions R1-R3.
Prior-art MOSFET control is usually performed in two possible ways: open loop or closed loop.
The open loop control is often based on the usage of circuits that introduce delays to take into account the duration of the corresponding phases required to pass the various regions R1-R3. In fact, as shown in FIG. 4, in case of known charge currents with a constant value at least during each of the drive phases over the regions R1-R3, the boundaries between the regions R1/R2 and R2/R3 correspond approximately to determined time instants t1 and t2.
For example, in FIG. 5, each control signal IN1/IN2 is fed both to the driver 2001/2002 and to a delay chain, comprising for example two delay lines 204, in order to generate further control signals able to detect when a given phase has ended.
This approach has a simple implementation, but a drawback relates to the fact that process and temperature variations have to be taken into account to set the proper delay timing. Accordingly, margins should be taken into account in order to satisfy different conditions resulting in a reduced efficiency.
A second method for the gate control relies on a closed loop control.
As shown in FIG. 6, the closed loop control may be based on a detection of the turn on/off regions of the power MOSFETs by monitoring the gate voltage of the power MOSFET, e.g., by means of two comparators 206 configured to compare the gate-source voltage VGS of the respective power MOSFET with threshold values Vref L and Vref H.
As shown in FIG. 4, there exists usually a correspondence between the gate-source voltage ranges and the different turn on/off regions R1-R3, and the information at the output of comparators 206 can thus be used as a feedback to control dedicated circuits for each specific phase.
Moreover, thanks to the closed loop nature, this implementation is able to adapt the control to process and temperature variations. Nevertheless, a drawback relates to the commutation delays of the comparators 206 that influence the effective duration of the phases, thereby limiting the bandwidth of the control loop.